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Ticket #14965: cpuid.txt

File cpuid.txt, 29.5 KB (added by sdford, 9 years ago)
Line 
1CPU 0:
2 vendor_id = "GenuineIntel"
3 version information (1/eax):
4 processor type = primary processor (0)
5 family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
6 model = 0xa (10)
7 stepping id = 0x1 (1)
8 extended family = 0x0 (0)
9 extended model = 0x2 (2)
10 (simple synth) = Intel Core i5-2000 / Core i7-2000 / Mobile Core i3-2000 / Mobile Core i5-2000 / Mobile Core i7-2000 / Pentium G500/G600/G800 / Celeron G400/G500/700/800/B800 / Xeon E3-1200 (Sandy Bridge), 32nm
11 miscellaneous (1/ebx):
12 process local APIC physical ID = 0x0 (0)
13 cpu count = 0x0 (0)
14 CLFLUSH line size = 0x8 (8)
15 brand index = 0x0 (0)
16 brand id = 0x00 (0): unknown
17 feature information (1/edx):
18 x87 FPU on chip = true
19 virtual-8086 mode enhancement = true
20 debugging extensions = true
21 page size extensions = true
22 time stamp counter = true
23 RDMSR and WRMSR support = true
24 physical address extensions = true
25 machine check exception = true
26 CMPXCHG8B inst. = true
27 APIC on chip = true
28 SYSENTER and SYSEXIT = true
29 memory type range registers = true
30 PTE global bit = true
31 machine check architecture = true
32 conditional move/compare instruction = true
33 page attribute table = true
34 page size extension = true
35 processor serial number = false
36 CLFLUSH instruction = true
37 debug store = false
38 thermal monitor and clock ctrl = false
39 MMX Technology = true
40 FXSAVE/FXRSTOR = true
41 SSE extensions = true
42 SSE2 extensions = true
43 self snoop = true
44 hyper-threading / multi-core supported = false
45 therm. monitor = false
46 IA64 = false
47 pending break event = false
48 feature information (1/ecx):
49 PNI/SSE3: Prescott New Instructions = true
50 PCLMULDQ instruction = true
51 64-bit debug store = false
52 MONITOR/MWAIT = false
53 CPL-qualified debug store = false
54 VMX: virtual machine extensions = true
55 SMX: safer mode extensions = false
56 Enhanced Intel SpeedStep Technology = false
57 thermal monitor 2 = false
58 SSSE3 extensions = true
59 context ID: adaptive or shared L1 data = false
60 FMA instruction = false
61 CMPXCHG16B instruction = true
62 xTPR disable = false
63 perfmon and debug = false
64 process context identifiers = true
65 direct cache access = false
66 SSE4.1 extensions = true
67 SSE4.2 extensions = true
68 extended xAPIC support = true
69 MOVBE instruction = false
70 POPCNT instruction = true
71 time stamp counter deadline = true
72 AES instruction = true
73 XSAVE/XSTOR states = true
74 OS-enabled XSAVE/XSTOR = true
75 AVX: advanced vector extensions = true
76 F16C half-precision convert instruction = false
77 RDRAND instruction = false
78 hypervisor guest status = true
79 cache and TLB information (2):
80 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines
81 0x30: L1 cache: 32K, 8-way, 64 byte lines
82 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
83 processor serial number: 0002-06A1-0000-0000-0000-0000
84 deterministic cache parameters (4):
85 --- cache 0 ---
86 cache type = data cache (1)
87 cache level = 0x1 (1)
88 self-initializing cache level = true
89 fully associative cache = false
90 extra threads sharing this cache = 0x0 (0)
91 extra processor cores on this die = 0x0 (0)
92 system coherency line size = 0x3f (63)
93 physical line partitions = 0x0 (0)
94 ways of associativity = 0x7 (7)
95 WBINVD/INVD behavior on lower caches = true
96 inclusive to lower caches = false
97 complex cache indexing = false
98 number of sets - 1 (s) = 63
99 --- cache 1 ---
100 cache type = instruction cache (2)
101 cache level = 0x1 (1)
102 self-initializing cache level = true
103 fully associative cache = false
104 extra threads sharing this cache = 0x0 (0)
105 extra processor cores on this die = 0x0 (0)
106 system coherency line size = 0x3f (63)
107 physical line partitions = 0x0 (0)
108 ways of associativity = 0x7 (7)
109 WBINVD/INVD behavior on lower caches = true
110 inclusive to lower caches = false
111 complex cache indexing = false
112 number of sets - 1 (s) = 63
113 --- cache 2 ---
114 cache type = unified cache (3)
115 cache level = 0x2 (2)
116 self-initializing cache level = true
117 fully associative cache = false
118 extra threads sharing this cache = 0x0 (0)
119 extra processor cores on this die = 0x0 (0)
120 system coherency line size = 0x3f (63)
121 physical line partitions = 0x0 (0)
122 ways of associativity = 0xf (15)
123 WBINVD/INVD behavior on lower caches = true
124 inclusive to lower caches = false
125 complex cache indexing = false
126 number of sets - 1 (s) = 4095
127 MONITOR/MWAIT (5):
128 smallest monitor-line size (bytes) = 0x0 (0)
129 largest monitor-line size (bytes) = 0x0 (0)
130 enum of Monitor-MWAIT exts supported = true
131 supports intrs as break-event for MWAIT = true
132 number of C0 sub C-states using MWAIT = 0x0 (0)
133 number of C1 sub C-states using MWAIT = 0x0 (0)
134 number of C2 sub C-states using MWAIT = 0x0 (0)
135 number of C3 sub C-states using MWAIT = 0x0 (0)
136 number of C4 sub C-states using MWAIT = 0x0 (0)
137 number of C5 sub C-states using MWAIT = 0x0 (0)
138 number of C6 sub C-states using MWAIT = 0x0 (0)
139 number of C7 sub C-states using MWAIT = 0x0 (0)
140 Thermal and Power Management Features (6):
141 digital thermometer = false
142 Intel Turbo Boost Technology = false
143 ARAT always running APIC timer = false
144 PLN power limit notification = false
145 ECMD extended clock modulation duty = false
146 PTM package thermal management = false
147 digital thermometer thresholds = 0x0 (0)
148 ACNT/MCNT supported performance measure = false
149 ACNT2 available = false
150 performance-energy bias capability = false
151 extended feature flags (7):
152 FSGSBASE instructions = false
153 IA32_TSC_ADJUST MSR supported = false
154 BMI instruction = false
155 HLE hardware lock elision = false
156 AVX2: advanced vector extensions 2 = false
157 SMEP supervisor mode exec protection = false
158 BMI2 instructions = false
159 enhanced REP MOVSB/STOSB = false
160 INVPCID instruction = false
161 RTM: restricted transactional memory = false
162 QM: quality of service monitoring = false
163 deprecated FPU CS/DS = false
164 intel memory protection extensions = false
165 AVX512F: AVX-512 foundation instructions = false
166 RDSEED instruction = false
167 ADX instructions = false
168 SMAP: supervisor mode access prevention = false
169 Intel processor trace = false
170 AVX512PF: prefetch instructions = false
171 AVX512ER: exponent & reciprocal instrs = false
172 AVX512CD: conflict detection instrs = false
173 SHA instructions = false
174 PREFETCHWT1 = false
175 Direct Cache Access Parameters (9):
176 PLATFORM_DCA_CAP MSR bits = 0
177 Architecture Performance Monitoring Features (0xa/eax):
178 version ID = 0x0 (0)
179 number of counters per logical processor = 0x0 (0)
180 bit width of counter = 0x0 (0)
181 length of EBX bit vector = 0x0 (0)
182 Architecture Performance Monitoring Features (0xa/ebx):
183 core cycle event not available = false
184 instruction retired event not available = false
185 reference cycles event not available = false
186 last-level cache ref event not available = false
187 last-level cache miss event not avail = false
188 branch inst retired event not available = false
189 branch mispred retired event not avail = false
190 Architecture Performance Monitoring Features (0xa/edx):
191 number of fixed counters = 0x0 (0)
192 bit width of fixed counters = 0x0 (0)
193 XSAVE features (0xd/0):
194 XCR0 lower 32 bits valid bit field mask = 0x00000007
195 bytes required by fields in XCR0 = 0x00000340 (832)
196 bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
197 XCR0 upper 32 bits valid bit field mask = 0x00000000
198 YMM features (0xd/2):
199 YMM save state byte size = 0x00000100 (256)
200 YMM save state byte offset = 0x00000240 (576)
201 LWP features (0xd/0x3e):
202 LWP save state byte size = 0x00000000 (0)
203 LWP save state byte offset = 0x00000000 (0)
204 hypervisor_id = "KVMKVMKVM "
205 hypervisor features (0x40000001/eax):
206 kvmclock available at MSR 0x11 = true
207 delays unnecessary for PIO ops = true
208 mmu_op = false
209 kvmclock available a MSR 0x4b564d00 = true
210 async pf enable available by MSR = true
211 steal clock supported = true
212 guest EOI optimization enabled = true
213 stable: no guest per-cpu warps expected = true
214 extended feature flags (0x80000001/edx):
215 SYSCALL and SYSRET instructions = true
216 execution disable = true
217 1-GB large page support = true
218 RDTSCP = true
219 64-bit extensions technology available = true
220 Intel feature flags (0x80000001/ecx):
221 LAHF/SAHF supported in 64-bit mode = true
222 LZCNT advanced bit manipulation = false
223 3DNow! PREFETCH/PREFETCHW instructions = false
224 brand = "Intel Xeon E312xx (Sandy Bridge)"
225 L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
226 instruction # entries = 0xff (255)
227 instruction associativity = 0x1 (1)
228 data # entries = 0xff (255)
229 data associativity = 0x1 (1)
230 L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
231 instruction # entries = 0xff (255)
232 instruction associativity = 0x1 (1)
233 data # entries = 0xff (255)
234 data associativity = 0x1 (1)
235 L1 data cache information (0x80000005/ecx):
236 line size (bytes) = 0x40 (64)
237 lines per tag = 0x1 (1)
238 associativity = 0x2 (2)
239 size (Kb) = 0x40 (64)
240 L1 instruction cache information (0x80000005/edx):
241 line size (bytes) = 0x40 (64)
242 lines per tag = 0x1 (1)
243 associativity = 0x2 (2)
244 size (Kb) = 0x40 (64)
245 L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
246 instruction # entries = 0x0 (0)
247 instruction associativity = L2 off (0)
248 data # entries = 0x0 (0)
249 data associativity = L2 off (0)
250 L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
251 instruction # entries = 0x200 (512)
252 instruction associativity = 4-way (4)
253 data # entries = 0x200 (512)
254 data associativity = 4-way (4)
255 L2 unified cache information (0x80000006/ecx):
256 line size (bytes) = 0x40 (64)
257 lines per tag = 0x1 (1)
258 associativity = 16-way (8)
259 size (Kb) = 0x200 (512)
260 L3 cache information (0x80000006/edx):
261 line size (bytes) = 0x0 (0)
262 lines per tag = 0x0 (0)
263 associativity = L2 off (0)
264 size (in 512Kb units) = 0x0 (0)
265 Advanced Power Management Features (0x80000007/edx):
266 temperature sensing diode = false
267 frequency ID (FID) control = false
268 voltage ID (VID) control = false
269 thermal trip (TTP) = false
270 thermal monitor (TM) = false
271 software thermal control (STC) = false
272 100 MHz multiplier control = false
273 hardware P-State control = false
274 TscInvariant = false
275 Physical Address and Linear Address Size (0x80000008/eax):
276 maximum physical address bits = 0x28 (40)
277 maximum linear (virtual) address bits = 0x30 (48)
278 maximum guest physical address bits = 0x0 (0)
279 Logical CPU cores (0x80000008/ecx):
280 number of CPU cores - 1 = 0x0 (0)
281 ApicIdCoreIdSize = 0x0 (0)
282 SVM Secure Virtual Machine (0x8000000a/eax):
283 SvmRev: SVM revision = 0x0 (0)
284 SVM Secure Virtual Machine (0x8000000a/edx):
285 nested paging = false
286 LBR virtualization = false
287 SVM lock = false
288 NRIP save = false
289 MSR based TSC rate control = false
290 VMCB clean bits support = false
291 flush by ASID = false
292 decode assists = false
293 SSSE3/SSE5 opcode set disable = false
294 pause intercept filter = false
295 pause filter threshold = false
296 NASID: number of address space identifiers = 0x0 (0):
297 (multi-processing synth): none
298 (multi-processing method): Intel leaf 1/4
299 (APIC widths synth): CORE_width=0 SMT_width=16
300 (APIC synth): PKG_ID=8 CORE_ID=8 SMT_ID=0
301 (synth) = Intel Xeon E3-1200 (Sandy Bridge), 32nm
302CPU 1:
303 vendor_id = "GenuineIntel"
304 version information (1/eax):
305 processor type = primary processor (0)
306 family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
307 model = 0xa (10)
308 stepping id = 0x1 (1)
309 extended family = 0x0 (0)
310 extended model = 0x2 (2)
311 (simple synth) = Intel Core i5-2000 / Core i7-2000 / Mobile Core i3-2000 / Mobile Core i5-2000 / Mobile Core i7-2000 / Pentium G500/G600/G800 / Celeron G400/G500/700/800/B800 / Xeon E3-1200 (Sandy Bridge), 32nm
312 miscellaneous (1/ebx):
313 process local APIC physical ID = 0x1 (1)
314 cpu count = 0x0 (0)
315 CLFLUSH line size = 0x8 (8)
316 brand index = 0x0 (0)
317 brand id = 0x00 (0): unknown
318 feature information (1/edx):
319 x87 FPU on chip = true
320 virtual-8086 mode enhancement = true
321 debugging extensions = true
322 page size extensions = true
323 time stamp counter = true
324 RDMSR and WRMSR support = true
325 physical address extensions = true
326 machine check exception = true
327 CMPXCHG8B inst. = true
328 APIC on chip = true
329 SYSENTER and SYSEXIT = true
330 memory type range registers = true
331 PTE global bit = true
332 machine check architecture = true
333 conditional move/compare instruction = true
334 page attribute table = true
335 page size extension = true
336 processor serial number = false
337 CLFLUSH instruction = true
338 debug store = false
339 thermal monitor and clock ctrl = false
340 MMX Technology = true
341 FXSAVE/FXRSTOR = true
342 SSE extensions = true
343 SSE2 extensions = true
344 self snoop = true
345 hyper-threading / multi-core supported = false
346 therm. monitor = false
347 IA64 = false
348 pending break event = false
349 feature information (1/ecx):
350 PNI/SSE3: Prescott New Instructions = true
351 PCLMULDQ instruction = true
352 64-bit debug store = false
353 MONITOR/MWAIT = false
354 CPL-qualified debug store = false
355 VMX: virtual machine extensions = true
356 SMX: safer mode extensions = false
357 Enhanced Intel SpeedStep Technology = false
358 thermal monitor 2 = false
359 SSSE3 extensions = true
360 context ID: adaptive or shared L1 data = false
361 FMA instruction = false
362 CMPXCHG16B instruction = true
363 xTPR disable = false
364 perfmon and debug = false
365 process context identifiers = true
366 direct cache access = false
367 SSE4.1 extensions = true
368 SSE4.2 extensions = true
369 extended xAPIC support = true
370 MOVBE instruction = false
371 POPCNT instruction = true
372 time stamp counter deadline = true
373 AES instruction = true
374 XSAVE/XSTOR states = true
375 OS-enabled XSAVE/XSTOR = true
376 AVX: advanced vector extensions = true
377 F16C half-precision convert instruction = false
378 RDRAND instruction = false
379 hypervisor guest status = true
380 cache and TLB information (2):
381 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines
382 0x30: L1 cache: 32K, 8-way, 64 byte lines
383 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
384 processor serial number: 0002-06A1-0000-0000-0000-0000
385 deterministic cache parameters (4):
386 --- cache 0 ---
387 cache type = data cache (1)
388 cache level = 0x1 (1)
389 self-initializing cache level = true
390 fully associative cache = false
391 extra threads sharing this cache = 0x0 (0)
392 extra processor cores on this die = 0x0 (0)
393 system coherency line size = 0x3f (63)
394 physical line partitions = 0x0 (0)
395 ways of associativity = 0x7 (7)
396 WBINVD/INVD behavior on lower caches = true
397 inclusive to lower caches = false
398 complex cache indexing = false
399 number of sets - 1 (s) = 63
400 --- cache 1 ---
401 cache type = instruction cache (2)
402 cache level = 0x1 (1)
403 self-initializing cache level = true
404 fully associative cache = false
405 extra threads sharing this cache = 0x0 (0)
406 extra processor cores on this die = 0x0 (0)
407 system coherency line size = 0x3f (63)
408 physical line partitions = 0x0 (0)
409 ways of associativity = 0x7 (7)
410 WBINVD/INVD behavior on lower caches = true
411 inclusive to lower caches = false
412 complex cache indexing = false
413 number of sets - 1 (s) = 63
414 --- cache 2 ---
415 cache type = unified cache (3)
416 cache level = 0x2 (2)
417 self-initializing cache level = true
418 fully associative cache = false
419 extra threads sharing this cache = 0x0 (0)
420 extra processor cores on this die = 0x0 (0)
421 system coherency line size = 0x3f (63)
422 physical line partitions = 0x0 (0)
423 ways of associativity = 0xf (15)
424 WBINVD/INVD behavior on lower caches = true
425 inclusive to lower caches = false
426 complex cache indexing = false
427 number of sets - 1 (s) = 4095
428 MONITOR/MWAIT (5):
429 smallest monitor-line size (bytes) = 0x0 (0)
430 largest monitor-line size (bytes) = 0x0 (0)
431 enum of Monitor-MWAIT exts supported = true
432 supports intrs as break-event for MWAIT = true
433 number of C0 sub C-states using MWAIT = 0x0 (0)
434 number of C1 sub C-states using MWAIT = 0x0 (0)
435 number of C2 sub C-states using MWAIT = 0x0 (0)
436 number of C3 sub C-states using MWAIT = 0x0 (0)
437 number of C4 sub C-states using MWAIT = 0x0 (0)
438 number of C5 sub C-states using MWAIT = 0x0 (0)
439 number of C6 sub C-states using MWAIT = 0x0 (0)
440 number of C7 sub C-states using MWAIT = 0x0 (0)
441 Thermal and Power Management Features (6):
442 digital thermometer = false
443 Intel Turbo Boost Technology = false
444 ARAT always running APIC timer = false
445 PLN power limit notification = false
446 ECMD extended clock modulation duty = false
447 PTM package thermal management = false
448 digital thermometer thresholds = 0x0 (0)
449 ACNT/MCNT supported performance measure = false
450 ACNT2 available = false
451 performance-energy bias capability = false
452 extended feature flags (7):
453 FSGSBASE instructions = false
454 IA32_TSC_ADJUST MSR supported = false
455 BMI instruction = false
456 HLE hardware lock elision = false
457 AVX2: advanced vector extensions 2 = false
458 SMEP supervisor mode exec protection = false
459 BMI2 instructions = false
460 enhanced REP MOVSB/STOSB = false
461 INVPCID instruction = false
462 RTM: restricted transactional memory = false
463 QM: quality of service monitoring = false
464 deprecated FPU CS/DS = false
465 intel memory protection extensions = false
466 AVX512F: AVX-512 foundation instructions = false
467 RDSEED instruction = false
468 ADX instructions = false
469 SMAP: supervisor mode access prevention = false
470 Intel processor trace = false
471 AVX512PF: prefetch instructions = false
472 AVX512ER: exponent & reciprocal instrs = false
473 AVX512CD: conflict detection instrs = false
474 SHA instructions = false
475 PREFETCHWT1 = false
476 Direct Cache Access Parameters (9):
477 PLATFORM_DCA_CAP MSR bits = 0
478 Architecture Performance Monitoring Features (0xa/eax):
479 version ID = 0x0 (0)
480 number of counters per logical processor = 0x0 (0)
481 bit width of counter = 0x0 (0)
482 length of EBX bit vector = 0x0 (0)
483 Architecture Performance Monitoring Features (0xa/ebx):
484 core cycle event not available = false
485 instruction retired event not available = false
486 reference cycles event not available = false
487 last-level cache ref event not available = false
488 last-level cache miss event not avail = false
489 branch inst retired event not available = false
490 branch mispred retired event not avail = false
491 Architecture Performance Monitoring Features (0xa/edx):
492 number of fixed counters = 0x0 (0)
493 bit width of fixed counters = 0x0 (0)
494 XSAVE features (0xd/0):
495 XCR0 lower 32 bits valid bit field mask = 0x00000007
496 bytes required by fields in XCR0 = 0x00000340 (832)
497 bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
498 XCR0 upper 32 bits valid bit field mask = 0x00000000
499 YMM features (0xd/2):
500 YMM save state byte size = 0x00000100 (256)
501 YMM save state byte offset = 0x00000240 (576)
502 LWP features (0xd/0x3e):
503 LWP save state byte size = 0x00000000 (0)
504 LWP save state byte offset = 0x00000000 (0)
505 hypervisor_id = "KVMKVMKVM "
506 hypervisor features (0x40000001/eax):
507 kvmclock available at MSR 0x11 = true
508 delays unnecessary for PIO ops = true
509 mmu_op = false
510 kvmclock available a MSR 0x4b564d00 = true
511 async pf enable available by MSR = true
512 steal clock supported = true
513 guest EOI optimization enabled = true
514 stable: no guest per-cpu warps expected = true
515 extended feature flags (0x80000001/edx):
516 SYSCALL and SYSRET instructions = true
517 execution disable = true
518 1-GB large page support = true
519 RDTSCP = true
520 64-bit extensions technology available = true
521 Intel feature flags (0x80000001/ecx):
522 LAHF/SAHF supported in 64-bit mode = true
523 LZCNT advanced bit manipulation = false
524 3DNow! PREFETCH/PREFETCHW instructions = false
525 brand = "Intel Xeon E312xx (Sandy Bridge)"
526 L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
527 instruction # entries = 0xff (255)
528 instruction associativity = 0x1 (1)
529 data # entries = 0xff (255)
530 data associativity = 0x1 (1)
531 L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
532 instruction # entries = 0xff (255)
533 instruction associativity = 0x1 (1)
534 data # entries = 0xff (255)
535 data associativity = 0x1 (1)
536 L1 data cache information (0x80000005/ecx):
537 line size (bytes) = 0x40 (64)
538 lines per tag = 0x1 (1)
539 associativity = 0x2 (2)
540 size (Kb) = 0x40 (64)
541 L1 instruction cache information (0x80000005/edx):
542 line size (bytes) = 0x40 (64)
543 lines per tag = 0x1 (1)
544 associativity = 0x2 (2)
545 size (Kb) = 0x40 (64)
546 L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
547 instruction # entries = 0x0 (0)
548 instruction associativity = L2 off (0)
549 data # entries = 0x0 (0)
550 data associativity = L2 off (0)
551 L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
552 instruction # entries = 0x200 (512)
553 instruction associativity = 4-way (4)
554 data # entries = 0x200 (512)
555 data associativity = 4-way (4)
556 L2 unified cache information (0x80000006/ecx):
557 line size (bytes) = 0x40 (64)
558 lines per tag = 0x1 (1)
559 associativity = 16-way (8)
560 size (Kb) = 0x200 (512)
561 L3 cache information (0x80000006/edx):
562 line size (bytes) = 0x0 (0)
563 lines per tag = 0x0 (0)
564 associativity = L2 off (0)
565 size (in 512Kb units) = 0x0 (0)
566 Advanced Power Management Features (0x80000007/edx):
567 temperature sensing diode = false
568 frequency ID (FID) control = false
569 voltage ID (VID) control = false
570 thermal trip (TTP) = false
571 thermal monitor (TM) = false
572 software thermal control (STC) = false
573 100 MHz multiplier control = false
574 hardware P-State control = false
575 TscInvariant = false
576 Physical Address and Linear Address Size (0x80000008/eax):
577 maximum physical address bits = 0x28 (40)
578 maximum linear (virtual) address bits = 0x30 (48)
579 maximum guest physical address bits = 0x0 (0)
580 Logical CPU cores (0x80000008/ecx):
581 number of CPU cores - 1 = 0x0 (0)
582 ApicIdCoreIdSize = 0x0 (0)
583 SVM Secure Virtual Machine (0x8000000a/eax):
584 SvmRev: SVM revision = 0x0 (0)
585 SVM Secure Virtual Machine (0x8000000a/edx):
586 nested paging = false
587 LBR virtualization = false
588 SVM lock = false
589 NRIP save = false
590 MSR based TSC rate control = false
591 VMCB clean bits support = false
592 flush by ASID = false
593 decode assists = false
594 SSSE3/SSE5 opcode set disable = false
595 pause intercept filter = false
596 pause filter threshold = false
597 NASID: number of address space identifiers = 0x0 (0):
598 (multi-processing synth): none
599 (multi-processing method): Intel leaf 1/4
600 (APIC widths synth): CORE_width=0 SMT_width=16
601 (APIC synth): PKG_ID=65544 CORE_ID=65544 SMT_ID=1
602 (synth) = Intel Xeon E3-1200 (Sandy Bridge), 32nm

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