VirtualBox

Ticket #12350: Coreinfo.txt

File Coreinfo.txt, 5.7 KB (added by tuhinchakravorty, 9 years ago)
Line 
1
2Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz
3Intel64 Family 6 Model 60 Stepping 3, GenuineIntel
4Microcode signature: 0000001C
5HTT * Hyperthreading enabled
6HYPERVISOR - Hypervisor is present
7VMX * Supports Intel hardware-assisted virtualization
8SVM - Supports AMD hardware-assisted virtualization
9X64 * Supports 64-bit mode
10
11SMX - Supports Intel trusted execution
12SKINIT - Supports AMD SKINIT
13
14NX * Supports no-execute page protection
15SMEP * Supports Supervisor Mode Execution Prevention
16SMAP - Supports Supervisor Mode Access Prevention
17PAGE1GB * Supports 1 GB large pages
18PAE * Supports > 32-bit physical addresses
19PAT * Supports Page Attribute Table
20PSE * Supports 4 MB pages
21PSE36 * Supports > 32-bit address 4 MB pages
22PGE * Supports global bit in page tables
23SS * Supports bus snooping for cache operations
24VME * Supports Virtual-8086 mode
25RDWRFSGSBASE * Supports direct GS/FS base access
26
27FPU * Implements i387 floating point instructions
28MMX * Supports MMX instruction set
29MMXEXT - Implements AMD MMX extensions
303DNOW - Supports 3DNow! instructions
313DNOWEXT - Supports 3DNow! extension instructions
32SSE * Supports Streaming SIMD Extensions
33SSE2 * Supports Streaming SIMD Extensions 2
34SSE3 * Supports Streaming SIMD Extensions 3
35SSSE3 * Supports Supplemental SIMD Extensions 3
36SSE4a - Supports Streaming SIMDR Extensions 4a
37SSE4.1 * Supports Streaming SIMD Extensions 4.1
38SSE4.2 * Supports Streaming SIMD Extensions 4.2
39
40AES * Supports AES extensions
41AVX * Supports AVX intruction extensions
42FMA * Supports FMA extensions using YMM state
43MSR * Implements RDMSR/WRMSR instructions
44MTRR * Supports Memory Type Range Registers
45XSAVE * Supports XSAVE/XRSTOR instructions
46OSXSAVE * Supports XSETBV/XGETBV instructions
47RDRAND * Supports RDRAND instruction
48RDSEED - Supports RDSEED instruction
49
50CMOV * Supports CMOVcc instruction
51CLFSH * Supports CLFLUSH instruction
52CX8 * Supports compare and exchange 8-byte instructions
53CX16 * Supports CMPXCHG16B instruction
54BMI1 * Supports bit manipulation extensions 1
55BMI2 * Supports bit manipulation extensions 2
56ADX - Supports ADCX/ADOX instructions
57DCA - Supports prefetch from memory-mapped device
58F16C * Supports half-precision instruction
59FXSR * Supports FXSAVE/FXSTOR instructions
60FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
61MONITOR * Supports MONITOR and MWAIT instructions
62MOVBE * Supports MOVBE instruction
63ERMSB * Supports Enhanced REP MOVSB/STOSB
64PCLMULDQ * Supports PCLMULDQ instruction
65POPCNT * Supports POPCNT instruction
66LZCNT * Supports LZCNT instruction
67SEP * Supports fast system call instructions
68LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
69HLE - Supports Hardware Lock Elision instructions
70RTM - Supports Restricted Transactional Memory instructions
71
72DE * Supports I/O breakpoints including CR4.DE
73DTES64 * Can write history of 64-bit branch addresses
74DS * Implements memory-resident debug buffer
75DS-CPL * Supports Debug Store feature with CPL
76PCID * Supports PCIDs and settable CR4.PCIDE
77INVPCID * Supports INVPCID instruction
78PDCM * Supports Performance Capabilities MSR
79RDTSCP * Supports RDTSCP instruction
80TSC * Supports RDTSC instruction
81TSC-DEADLINE * Local APIC supports one-shot deadline timer
82TSC-INVARIANT * TSC runs at constant rate
83xTPR * Supports disabling task priority messages
84
85EIST * Supports Enhanced Intel Speedstep
86ACPI * Implements MSR for power management
87TM * Implements thermal monitor circuitry
88TM2 * Implements Thermal Monitor 2 control
89APIC * Implements software-accessible local APIC
90x2APIC * Supports x2APIC
91
92CNXT-ID - L1 data cache mode adaptive or BIOS
93
94MCE * Supports Machine Check, INT18 and CR4.MCE
95MCA * Implements Machine Check Architecture
96PBE * Supports use of FERR#/PBE# pin
97
98PSN - Implements 96-bit processor serial number
99
100PREFETCHW * Supports PREFETCHW instruction
101
102Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).
103
104Logical to Physical Processor Map:
105**------ Physical Processor 0 (Hyperthreaded)
106--**---- Physical Processor 1 (Hyperthreaded)
107----**-- Physical Processor 2 (Hyperthreaded)
108------** Physical Processor 3 (Hyperthreaded)
109
110Logical Processor to Socket Map:
111******** Socket 0
112
113Logical Processor to NUMA Node Map:
114******** NUMA Node 0
115
116No NUMA nodes.
117
118Logical Processor to Cache Map:
119**------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
120**------ Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
121**------ Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
122******** Unified Cache 1, Level 3, 6 MB, Assoc 12, LineSize 64
123--**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
124--**---- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
125--**---- Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
126----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
127----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
128----**-- Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
129------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
130------** Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
131------** Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
132
133Logical Processor to Group Map:
134******** Group 0

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy