| 1 |
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| 2 | Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz
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| 3 | Intel64 Family 6 Model 60 Stepping 3, GenuineIntel
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| 4 | Microcode signature: 0000001C
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| 5 | HTT * Hyperthreading enabled
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| 6 | HYPERVISOR - Hypervisor is present
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| 7 | VMX * Supports Intel hardware-assisted virtualization
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| 8 | SVM - Supports AMD hardware-assisted virtualization
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| 9 | X64 * Supports 64-bit mode
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| 10 |
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| 11 | SMX - Supports Intel trusted execution
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| 12 | SKINIT - Supports AMD SKINIT
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| 13 |
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| 14 | NX * Supports no-execute page protection
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| 15 | SMEP * Supports Supervisor Mode Execution Prevention
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| 16 | SMAP - Supports Supervisor Mode Access Prevention
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| 17 | PAGE1GB * Supports 1 GB large pages
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| 18 | PAE * Supports > 32-bit physical addresses
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| 19 | PAT * Supports Page Attribute Table
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| 20 | PSE * Supports 4 MB pages
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| 21 | PSE36 * Supports > 32-bit address 4 MB pages
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| 22 | PGE * Supports global bit in page tables
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| 23 | SS * Supports bus snooping for cache operations
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| 24 | VME * Supports Virtual-8086 mode
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| 25 | RDWRFSGSBASE * Supports direct GS/FS base access
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| 26 |
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| 27 | FPU * Implements i387 floating point instructions
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| 28 | MMX * Supports MMX instruction set
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| 29 | MMXEXT - Implements AMD MMX extensions
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| 30 | 3DNOW - Supports 3DNow! instructions
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| 31 | 3DNOWEXT - Supports 3DNow! extension instructions
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| 32 | SSE * Supports Streaming SIMD Extensions
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| 33 | SSE2 * Supports Streaming SIMD Extensions 2
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| 34 | SSE3 * Supports Streaming SIMD Extensions 3
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| 35 | SSSE3 * Supports Supplemental SIMD Extensions 3
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| 36 | SSE4a - Supports Streaming SIMDR Extensions 4a
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| 37 | SSE4.1 * Supports Streaming SIMD Extensions 4.1
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| 38 | SSE4.2 * Supports Streaming SIMD Extensions 4.2
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| 39 |
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| 40 | AES * Supports AES extensions
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| 41 | AVX * Supports AVX intruction extensions
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| 42 | FMA * Supports FMA extensions using YMM state
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| 43 | MSR * Implements RDMSR/WRMSR instructions
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| 44 | MTRR * Supports Memory Type Range Registers
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| 45 | XSAVE * Supports XSAVE/XRSTOR instructions
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| 46 | OSXSAVE * Supports XSETBV/XGETBV instructions
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| 47 | RDRAND * Supports RDRAND instruction
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| 48 | RDSEED - Supports RDSEED instruction
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| 49 |
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| 50 | CMOV * Supports CMOVcc instruction
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| 51 | CLFSH * Supports CLFLUSH instruction
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| 52 | CX8 * Supports compare and exchange 8-byte instructions
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| 53 | CX16 * Supports CMPXCHG16B instruction
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| 54 | BMI1 * Supports bit manipulation extensions 1
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| 55 | BMI2 * Supports bit manipulation extensions 2
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| 56 | ADX - Supports ADCX/ADOX instructions
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| 57 | DCA - Supports prefetch from memory-mapped device
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| 58 | F16C * Supports half-precision instruction
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| 59 | FXSR * Supports FXSAVE/FXSTOR instructions
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| 60 | FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
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| 61 | MONITOR * Supports MONITOR and MWAIT instructions
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| 62 | MOVBE * Supports MOVBE instruction
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| 63 | ERMSB * Supports Enhanced REP MOVSB/STOSB
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| 64 | PCLMULDQ * Supports PCLMULDQ instruction
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| 65 | POPCNT * Supports POPCNT instruction
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| 66 | LZCNT * Supports LZCNT instruction
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| 67 | SEP * Supports fast system call instructions
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| 68 | LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
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| 69 | HLE - Supports Hardware Lock Elision instructions
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| 70 | RTM - Supports Restricted Transactional Memory instructions
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| 71 |
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| 72 | DE * Supports I/O breakpoints including CR4.DE
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| 73 | DTES64 * Can write history of 64-bit branch addresses
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| 74 | DS * Implements memory-resident debug buffer
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| 75 | DS-CPL * Supports Debug Store feature with CPL
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| 76 | PCID * Supports PCIDs and settable CR4.PCIDE
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| 77 | INVPCID * Supports INVPCID instruction
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| 78 | PDCM * Supports Performance Capabilities MSR
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| 79 | RDTSCP * Supports RDTSCP instruction
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| 80 | TSC * Supports RDTSC instruction
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| 81 | TSC-DEADLINE * Local APIC supports one-shot deadline timer
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| 82 | TSC-INVARIANT * TSC runs at constant rate
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| 83 | xTPR * Supports disabling task priority messages
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| 84 |
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| 85 | EIST * Supports Enhanced Intel Speedstep
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| 86 | ACPI * Implements MSR for power management
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| 87 | TM * Implements thermal monitor circuitry
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| 88 | TM2 * Implements Thermal Monitor 2 control
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| 89 | APIC * Implements software-accessible local APIC
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| 90 | x2APIC * Supports x2APIC
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| 91 |
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| 92 | CNXT-ID - L1 data cache mode adaptive or BIOS
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| 93 |
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| 94 | MCE * Supports Machine Check, INT18 and CR4.MCE
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| 95 | MCA * Implements Machine Check Architecture
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| 96 | PBE * Supports use of FERR#/PBE# pin
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| 97 |
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| 98 | PSN - Implements 96-bit processor serial number
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| 99 |
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| 100 | PREFETCHW * Supports PREFETCHW instruction
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| 101 |
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| 102 | Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).
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| 103 |
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| 104 | Logical to Physical Processor Map:
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| 105 | **------ Physical Processor 0 (Hyperthreaded)
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| 106 | --**---- Physical Processor 1 (Hyperthreaded)
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| 107 | ----**-- Physical Processor 2 (Hyperthreaded)
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| 108 | ------** Physical Processor 3 (Hyperthreaded)
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| 109 |
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| 110 | Logical Processor to Socket Map:
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| 111 | ******** Socket 0
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| 112 |
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| 113 | Logical Processor to NUMA Node Map:
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| 114 | ******** NUMA Node 0
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| 115 |
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| 116 | No NUMA nodes.
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| 117 |
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| 118 | Logical Processor to Cache Map:
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| 119 | **------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
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| 120 | **------ Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
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| 121 | **------ Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
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| 122 | ******** Unified Cache 1, Level 3, 6 MB, Assoc 12, LineSize 64
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| 123 | --**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
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| 124 | --**---- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
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| 125 | --**---- Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
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| 126 | ----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
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| 127 | ----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
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| 128 | ----**-- Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
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| 129 | ------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
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| 130 | ------** Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
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| 131 | ------** Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
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| 132 |
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| 133 | Logical Processor to Group Map:
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| 134 | ******** Group 0
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